Antonios Gogios
Software Engineer
x86 Bootloader Stub: Secondary CPU initialization
2017
(WIP, text pending)
Illustrated Overview
1. Memory placement
The memory map of Fig. 1 summarizes the bootloader's placement in memory. Stage-1 is loaded by the BIOS at linear address 0x7C00. Stage-1 begins execution and in turn loads Stage-2 at 0x7E00 and jumps to it. The bootloader also maintains a stack beginning at 0x9FBFF, the highest free address for 16-bit real mode usage.
To access addresses higher than the first MB (0x100000 and up), Stage-2 requires to enable the A20 gate and subsequently switch to protected mode.
2. Boot disk structure and I/O methods
The boot disk uses a simple file system designed by myself for these tests. A C++ utility program I wrote is used to generate the disk image in accordance with the file system's structure (Fig. 2). To read the data from disk, the file system is navigated by the bootloader and BIOS interrupts are employed to extract the data and load it to memory.
3. Real mode debug utilities
While developing the bootloader stub I also implemented some basic real mode debugging utilities. They utilize BIOS interrupts and allow stepping through code and easily examining the contents of CPU registers and RAM (see Fig. 3).
4. Initializing secondary CPUs
Stage-2 begins by enabling the A20 gate and making the memory above 0x100000 accessible. However, so far the system has been executing in unicore mode. To enable hardware concurrency, the boot-strapping processor (BSP) requires to initialize the other application processors (APs). This is achieved by using inter-processor interrupts (IPIs) (see Fig. 4 for a sample breakdown).
I here implement the initialization algorithm described in Intel's documentation. In contemporary Linux, this algorithm is implemented through the function wakeup_secondary_cpu_via_init() in arch/x86/kernel/smpboot.c
(linked here).

Fig. 1: Memory map for bootloader

Fig. 2: Boot disk generation process

Fig. 3: A debug utilities test

Fig. 4: Broadcasting the INIT IPI to all Application Processors. The process is similar for issuing the STARTUP IPI.
(WIP, text pending)